February 7, 2022. Bristol, UK. DDC-I, a leading supplier of software and professional services for mission- and safety-critical applications, today announced that it will present a paper on multicore design considerations and optimization for safety-critical avionics at the Safety-Critical Systems Symposium (SSS’22). The 30th anniversary Symposium will be held in Bristol, UK from February 8-10 at the Bristol Royal Marriott Hotel and blended online as a live-streamed event through the SCSC website and the Whova application.
The Safety-Critical Systems Symposium comprises three days of live presented papers, including keynote presentations and submitted papers, with a 30-year retrospective and 30-year look ahead. There will also be an evening session on the Wednesday with additional talks. The Symposium is for all of those in the field of systems safety, including engineers, managers, consultants, students, researchers and regulators. It offers wide-ranging coverage of current safety topics with a focus on industrial experience, includes recent developments in the field and progress reports from the SCSC Working Groups, and covers all safety-related sectors including aerospace, defense, health, highways, marine, nuclear and rail.
“We are excited to be part of the 30th anniversary of the Safety-Critical Systems Symposium and look forward to bringing avionics designers up to speed on the latest developments in multicore technology,” said Greg Rose, vice president of marketing and product management at DDC-I. “Our presentation is a must see for avionics developers who want to utilize the latest multicore technology while meeting the worst-case execution requirements defined in the FAA’s CAST-32A position paper for Multi-core Processors. Our Deos SafeMC technology uniquely resolves the CAST-32A multicore objectives, enabling developers to achieve unmatched performance and determinism for safety-critical applications.”
Creating a multi-core platform for safety-critical avionics is the next major step for most avionics manufacturers. While multi-core processors are commonly used in most other markets, the avionics industry has taken years to trust multi-core technologies. Acceptance has been slow due to an avionics system’s stringent safety and deterministic requirements. As a result, years of study have been invested by certification authorities and industry suppliers to identify the issues multi-core processors pose for safety-critical systems. Formalized positions of these efforts are the FAA CAST-32A Positioning Paper, and EASA’s multi-core Certification Review Item (CRI). The crux of these papers (regarding software) focuses on bounding and controlling the interference patterns that exists when processor cores share resources.
This paper, scheduled for Thursday February 10 at 13:05, highlights the challenges of implementing multi-core processors for avionics developers. It will present Deos SafeMC and show how it helps address CAST-32A objectives by utilizing unique operating system features designed for minimizing and bounding contention issues within multi-core environments. Features such as cache partitioning, memory pooling and safe scheduling enable users to configure the memory architecture to minimize cache thrashing and schedule applications across all cores. Together, these capabilities enable developers to employ modern systems that orchestrate software applications such that conflicts over shared resources are minimized and the overall performance advantages of multicore processors can best be utilized.
Deos is a safety-critical embedded RTOS that employs patented cache partitioning, memory pools, and safe scheduling to deliver higher CPU utilization than any other certifiable safety-critical COTS RTOS on multi-core processors. First certified to DO-178 DAL A in 1998, Deos provides a FACE™ Conformant Safety Base Profile that features hard real-time response, time and space partitioning, and both ARINC-653 and POSIX interfaces.
SafeMC technology extends Deos’ advanced capabilities to multiple cores, enabling developers of safety-critical systems to achieve best in class multi-core performance without compromising safety-critical task response and guaranteed execution time. SafeMC employs a bound multiprocessing (BMP) extension of the symmetric multiprocessing architecture (SMP), safe scheduling, and cache partitioning to minimize cross-core contention and interference patterns that affect the performance, safety criticality and certifiability of multi-core systems. These features enable avionics systems developers to address issues that could impact the safety, performance and integrity of a software airborne system executing on Multi-Core Processors (MCP), as specified by the Certification Authorities Software Team (CAST) in its Position Paper CAST-32A for Multi-core Processors.
About DDC-I, Inc.
DDC-I, Inc. is a global supplier of real-time operating systems, software development tools, custom software development services, and legacy software system modernization solutions, with a primary focus on mission- and safety-critical applications. DDC-I’s customer base is an impressive “who’s who” in the commercial, military, aerospace, and safety-critical industries. DDC-I offers safety-critical real-time operating systems, compilers, integrated development environments and run-time systems for C, C++, and Ada application development. For more information regarding DDC-I products, contact DDC-I at 4545 E. Shea Blvd, Phoenix, AZ 85028; phone (602) 275-7172; fax (602) 252-6054; e-mail firstname.lastname@example.org or visit http://www.ddci.com/pr2201.